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Fix turn lanes bug (a test fix)

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This commit is contained in:
Victor Shcherb 2018-05-26 00:02:57 +02:00
parent f8246c5cf4
commit df88bf74be
3 changed files with 10 additions and 8 deletions
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4
OsmAnd-java/src/net/osmand/router/RouteResultPreparation.java
View file

@ -743,9 +743,9 @@ public class RouteResultPreparation {
} }
} }
} }
if(straightActiveLen == target.activeLen) { if(straightActiveBegin != -1 && straightActiveLen <= target.activeLen) {
active.activeStartIndex = straightActiveBegin; active.activeStartIndex = straightActiveBegin;
active.activeEndIndex = straightActiveBegin + target.activeLen - 1; active.activeEndIndex = straightActiveBegin + straightActiveLen - 1;
changed = true; changed = true;
} else { } else {
// cause the next-turn goes forward exclude left most and right most lane // cause the next-turn goes forward exclude left most and right most lane

10
OsmAnd-java/src/net/osmand/router/TurnType.java
View file

@ -416,11 +416,13 @@ public class TurnType {
public static int convertType(String lane) { public static int convertType(String lane) {
int turn; int turn;
// merge should be recognized as continue route (but it could displayed differently) // merge should be recognized as continue route (but it could displayed differently)
if (lane.equals("none") || lane.equals("through") if(lane.equals("merge_to_left")) {
|| lane.equals("merge_to_left")
|| lane.equals("merge_to_right")) {
turn = TurnType.C; turn = TurnType.C;
} else if (lane.equals("slight_right") ) { } else if(lane.equals("merge_to_right")) {
turn = TurnType.C;
} else if (lane.equals("none") || lane.equals("through")) {
turn = TurnType.C;
} else if (lane.equals("slight_right")) {
turn = TurnType.TSLR; turn = TurnType.TSLR;
} else if (lane.equals("slight_left") ) { } else if (lane.equals("slight_left") ) {
turn = TurnType.TSLL; turn = TurnType.TSLL;

4
OsmAnd-java/test/resources/test_turn_lanes.json
View file

@ -595,8 +595,8 @@
}, },
"expectedResults": { "expectedResults": {
"222244": "TL|TL|+C,TR", "222244": "TL|TL|+C,TR",
"222243": "TL|TL|+C|C|TSLR", "222243": "TL|TL|+C|+C|TSLR",
"222164": "TL|TL|+C|C" "222164": "TL|TL|+C|+C"
} }
}, },
{ {